1. Field of the Invention
The present invention relates to computer aided design of electronic circuits, and more particularly to the generation of a circuit level netlist from a logic level netlist of an integrated circuit.
2. Description of Related Art
The high cost of integrated circuit design has led to the development of circuits that are customized to perform a user-defined function. This class of circuits includes the gate array, which is an integrated circuit that includes an array of unwired logic gates that are customized at the metallization mask stage.
The design and layout sequence 30 for a customer designed gate array, which generally is known as a customer "option," is illustrated in FIG. 1. FIG. 1 also shows a connectivity check step 28 which follows the design and layout sequence 30. Integrated systems for performing the design and layout sequence of FIG. 1 are generally available, and include the FAIRCAD (Trademark) system of National Semiconductor Corporation, Santa Clara, Calif.
The design and layout sequence 30 generally begins with a schematic capture step 10 and the generation of logic netlist 12. The logic netlist 12 is a logic level description of the customer option, specifying the names of each individual occurrence or "instance" of macrocells in the customer option, pin utilization, and connectivity between the various macrocell instances. In the FAIRCAD system, the filename of the logic netlist 12 is GENNET.LIS. In performing the schematic capture step 10, the option designer works with a predetermined set of logical element symbols, interconnecting each instance of a logic element in the customer option as desired and specifying parameters for each instance. These parameters include power requirements and number of inputs and outputs desired. Schematic capture software suitable for operation on workstations or general purpose computers is separately available from such vendors as, for example, Silvar-Lisco, Inc. of Sunnyvale, Calif.
A pre-layout simulation 14 preferably is performed on the logic netlist 12 to confirm the logic functionality of the customer option. If the logic functionality is not satisfactory, the customer option is modified as necessary by repeating the schematic capture step 10. Another pre-layout simulation is performed on the modified logic netlist 12 to confirm the logic functionality of the redesigned customer option. Suitable simulation software systems for use on workstations or general purpose computers include the FAIRLOGS (Trademark) system, which is part of the FAIRCAD system available from National Semiconductor Corporation; and the VERILOGS (Trademark) system, available from Gateway Design Automation Corp., Westford, Mass.
Once the logic functionality of the customer option is confirmed, a placement and routing operation 16 is performed on the customer option, as represented in the logic netlist 12. Several files result from the placement and routing step 16, the most notable of which are a physical connectivity data file 17, a file 18 that provides the bias driver identification associated with every macro instance in the customer option, a file 19 that specifies the names of input I/O macro instances of the customer option using pulldown resistors, and a file 20 specifying the pad to signal name relationships for the customer option. In the FAIRCAD system, these files are known as DESIGN.DFF, DESIGN.BOV, DESIGN.MVA, AND XXAUTOPIN.S50 respectively. The physical connectivity data file 17, the bias driver identification file 18, and the I/O macro pulldown resistor definition file 19 are used in a post-processing step 22, discussed below. The pad - I/O signal relationship file 20 is generally used in a test verification operation that occurs after fabrication of the customer option. Placement and routing software systems for use on workstations or general purpose computers are available separately, and include the GARDS system available from Silvar-Lisco, Inc.
A post-layout simulation preferably is then done to confirm the timing characteristics of the physical connectivity, which is modified as necessary in an iterative process involving placement and routing step 16 and post-layout simulation step 21. The previously mentioned FAIRLOGS system and VERILOGS system are suitable for use in post-layout simulation.
Once the physical connectivity of the file 17 is confirmed, the physical connections are "databased" from the physical connectivity data file 17 in a post-processing operation 22 to produce a physical data base 24. The physical data base 24 preferably is produced in a suitable industry standard format, such as the CV format of the Computervision Corporation of Bedford, Mass. which is now a division of Prime Computer, Inc.; the APL format of the CAD/CAM Division of Schlumberger Technologies, Inc., Ann Arbor, Mich.; and the GDS format of the Calma Company of San Diego, Calif., now a division of Prime Computer, Inc.
The post-processing operation 22 requires many input files. Some of these input files are physical data base files contained in several different libraries. One set of input files is found in the macrocell library 2. The files of this set are for the various types of macrocells corresponding to the logic elements made available to the option designer. A macrocell is an elementary circuit used as a building block in the design of ASIC chips such as gate arrays and standard cells, and may have various power and input/output configurations. Macrocell libraries are available from a number of manufacturers, including National Semiconductor Corporation, which describes an ECL family of macrocells in a publication entitled FGA Series Macro Library for ASPECT (Trademark) ECL Gate Arrays, Revision No. 0.3, 1989. Another set of input files is found in the overlay library 4. The files of this set are for various metallization and contact layer definitions used in customizing an instance of a macrocell to a selected power configuration. Another set of input files is found in the bias generator library 6. The files of this set are for various standard bias generators.
Some of the input files to the post processing step 22 are generated in the placement and routing step 16, as described above. One of these files is the physical connectivity file 17 (DESIGN.DFF). Another input file, the bias driver identification file 18 (DESIGN.BOV), contains an identification of the bias netlist utilized by each single macro instance. Another input file, the I/O macro pulldown file 19 (DESIGN.MVA), defines the pulldown resistor utilization of the various input macros.
To ensure correct implementation of the customer option, a physical connectivity check must be done on the layout. Traditionally, physical connectivity checking was performed manually in a process called "plot checking." The physical data base files are used to print composite plots 26, which are reviewed by an integrated circuit engineer in a connectivity checking operation 28. Unfortunately, a plot check of, for example, an ECL (emitter-coupled logic) gate array design of 15,000 gate level complexity at a component level is time and resource intensive and subject to human error. The plot check is further complicated by the option designer's use of different configurations of each macrocell, due to different requirements for power and input/output combinations throughout the customer option.
The macrocell library 2, the overlay library 4, and the bias generator library 6 generally are created as follows. A circuit level netlist is prepared, either by being written directly by an engineer or generated automatically from a circuit schematic prepared by an engineer. The macrocell is laid out using computer tools, such as, for example, the SCALD (Trademark) system with the LED and LED2STREAM software, which is available from Valid Logic Systems, Inc. of San Jose, Calif. The resulting physical data base is compared with the circuit level netlist, also commonly with computer tools, to ensure consistency in continuity. Commercially available software suitable for performing the comparison includes the "Layout versus Schematic" system available from Cadence Design Systems, Inc. of Santa Clara, Calif.; and the "Network Consistency Check" system available from Silvar-Lisco, Inc.
Unfortunately, this technique is not effective for use on large circuit designs. The manual generation of a circuit schematic or a circuit level netlist for an entire customer option, which generally includes many macrocell instances in complex arrangements, is time and resource intensive and subject to human error. For an ECL (emitter-coupled logic) gate array design of 15,000 gate level complexity, for example, the manual generation of a circuit schematic netlist may be commercially impracticable.